1. Field of the Invention
The present invention relates generally to solid state memory devices and, more particularly, to the refresh requirements of dynamic random access memories (DRAM).
2. Description of the Background
The simplest configuration for a DRAM is a memory cell comprised of one transistor which operates in conjunction with a capacitor. The transistor is connected across a bit line and the capacitor, and is gated by a wordline. The other plate of the capacitor is connected to a common circuit plate. A write operation is performed by placing data on the bit line and gating the data into the capacitor with the wordline. A read operation is performed by precharging the bit line and raising the wordline. Charge sharing, occurring between the cell's capacitor and the bit line, changes the voltage on the bit line by between 5% and 30%, while the information in the cell is destroyed. Thus, a read operation must be accompanied by a write back to ensure the integrity of the data.
DRAM cells are extremely small because they require only a single transistor and a single capacitor. Therefore, very high density DRAMs can be fabricated. Densities can be increased even further by constructing the capacitor in a vertical direction, e.g., a trench capacitor, as opposed to a planar direction. Because of their high density, DRAMs can often be fabricated at lower costs than other types of memory cells.
One characteristic associated with DRAMs is that the voltage stored on the capacitor of an individual cell tends to dissipate over time as a result of leakage currents. Because the difference between a voltage which represents a logic 1 and a voltage which represents a logic 0 is very small, each cell of the DRAM must be periodically refreshed to ensure the accuracy of the data stored therein. Despite the need to refresh the data, DRAMs are widely used because of their lower cost.
A refresh operation generally comprises copying the data held in certain of the memory cells into one or more registers and then copying the data back into the memory cells from the registers. Traditionally, that refresh requirement has required additionally circuitry. A memory controller, or perhaps the system processor, intercedes between successive read and write operations to initiate the refresh in a forced manner. Forced refresh operations result in delaying subsequent read or write operations.
More recently, DRAMs have been proposed which have a self-refresh mode for executing the refresh process. In such DRAMs, a refresh signal does not need to be generated by the memory controller or system processor. DRAMs having self-refresh capability include a circuit specifically designed for initiating and carrying out the refresh operation.
Nevertheless, whether the refresh is initiated by a device external to the DRAM or internal to the DRAM, the systematic reading and writing back of information from each cell within the array consumes both power and time. Thus, the need exists, for adding intelligence to the refresh decision in a manner which does not unduly complicate the DRAM circuit.